One-week intensive course on
Hardware Description Lanuages for Synchronous Circuits

Gordon Pace, Koen Claessen

Exercises: Desining circuits in Verilog

Tuesday 5th September

Viperfree can be downloaded from here.

1. Events
A security device has three different input buttons labelled a, b and c. The output of the system on oes high once all three buttons have been pressed (in any order, and not necessarily at the same time).

Exercises

a. Write a behavioural description of this circuit in Verilo.

b. A more complex device turns on only when each button has been on for an odd number of clock cycles. Write a behavioural description for this circuit.

Hint: Remember to add a clock sinal to make the circuit sequential. You may assume that the inputs remain constant durin a clock cycle.
2. A Stack

Yesterday, you desined a stack structurally. Today you will desin the same circuit using Verilog.

Exercises

a. Desin a behavioural module describing a stack which can store 4 1-bit elements.

b. Implement your solution to yesterday's problem usin structural Verilo.

c. Test your implementation in (b) with respect to the behavioural description in (a) by buildin a test bench.

d. (*) Modify your solution to implement a 6 rather than 4 place stack.