Formal Verification of CHP Specifications with CADP - Illustration on an Asynchronous Network-on-Chip
Gwen SalaŁn, Wendelin Serwe, Yvain Thonnart, Pascal Vivet
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems ASYNC 2007 (Berkeley, California, USA), March 2007.
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architectures described in the high-level language CHP, by using model checking techniques provided by the CADP toolbox. Our proposal is based on an automatic translation from CHP into LOTOS, the process algebra used in CADP. A translator has been implemented, which handles full CHP including the specific probe operator.
The CADP toolbox capabilities allow the designer to verify properties
such as deadlock-freedom or protocol correctness on substantial
systems. Our approach has been successfully applied to formally verify
two complex designs. In this paper, we illustrate our technique on an
asynchronous Network-on-Chip architecture. Its formal verification
highlights the need to carefully design systems exhibiting
|Slides of P. Vivet's lecture at ASYNC'07|