Since November 2008, I am a post-doctorate researcher in the VASY project of the INRIA Rhône-Alpes research center. I study the verfication of asynchronous concurrent systems. I have already worked in this team during summer 2007.
From September 2007 to October 2008, I was post-doctorate researcher in the DeviceWare project team of the LIAMA sino-french laboratory. I was designing functional simulators of embedded systems, for embedded software validation. This lab is located in Beijing; it is part of INRIA. My chief was Vania Joloboff.
From December 2003 to June 2007, I have been working in the Synchronous team of the Verimag laboratory, in collaboration with the SPG team of STMicroelectronics. I was PhD student, and I got my PhD in March 2007. My advisor was Florence Maraninchi.
Research Topics and Publications
My main interest lies in the validation of asynchronous systems, using simulation, automatic test generation, or formal verification techniques. Functional models of Systems on Chips (SoCs) are generally written in SystemC using the TLM library. They are mainly used for the validation of the embedded software. Dynamic partial order reduction gives very good results on this kind of programs.
- Dynamic partial order reduction and automatic test generation
- Functional modeling of embedded systems, faithfulness of models
- Validation of embedded software and robustness checking
- Fast hardware emulation using SystemC, TLM and dynamic translation
- Generation of Executable Representation for
Processor Simulation with Dynamic Translation,
Song Jiajia, Hao Hongwei, Claude Helmstetter, and Vania Joloboff; CSSE'08 (paper, bibtex).
- SimSoC: A SystemC TLM integrated ISS for full
Claude Helmstetter and Vania Joloboff; APCCAS'08 (paper, bibtex).
- SystemC/TLM Semantics for Heterogeneous
Florence Maraninchi, Matthieu Moy, Jérôme Cornet, Laurent Maillet-Contoz, Claude Helmstetter, and Claus Traulsen; NEWCAS-TAISA 2008 (link to full text).
- A Comparison of Two SystemC/TLM Semantics for Formal Verification,
Claude Helmstetter and Olivier Ponsini; MEMOCODE'08 (link to full text, bibtex).
- PhD thesis: Validating Models of Systems-on-a-Chip in the Presence of Nondeterministic Schedulings and Loose Timings.
- Test Coverage for Loose Timing Annotations,
Claude Helmstetter, Florence Maraninchi, and Laurent Maillet-Contoz; FMICS'06, © Springer-Verlag 2007 (paper, slides, bibtex).
- Automatic Generation of Schedulings for Improving the
Test Coverage of Systems-on-a-Chip,
Claude Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz, and Matthieu Moy; FMCAD'06 (paper, slides, bibtex).
- During my PhD, I have developped the SystemC Runtime Verification Toolbox (SCRV). It is available for free, under the SystemC License.
- During my post-doctorate in Beijing, I have developped a embedded system simultor called SimSoC. If you are interested by this software, contact Vania Joloboff.
- A few files, maybe only useful for me:
- a script to compile the GNU ARM-elf cross-compiler tool-suite, same for MIPS (tested with binutils 2.17, gcc 4.1.1, and newlib 1.14.0)
- My emacs configuration files: claude.emacs.el and claude.emacs-customize.el
- Software Engineering Project
- 4 weeks project to train the students with Software Engineering by doing them realize a compiler for an imperative language, in 4-student team; 55 hours in January 2005 and in January 2006.
- Unix Training Course
- Initiation to computer science and UNIX; 9 hours in September 2004 and 12 hours in September 2005.